I have a fascination with analogue calculators and have a modest collection of slide rules which have shared aspects of in Micscape Lite articles. This interest extends into the early history of supercomputers. The earliest to me have more interest; both the technologies that were being pioneered and the people who designed and built them. The modern examples typically make use of thousands of desktop type chips and are awesome in their computational firepower. Apart from the typical 'go-faster designs' on the cladding of the huge array of cabinets, they seem have less character. At the time of writing the current fastest is the Japanese Fugaku which uses over 150 000 Fujitsu A64FX 48 core ARM based processors. It is bringing the computational power of supercomputers from petaFLOPS (10¹⁵) to exaFLOPS (10¹⁸). (If count distributed computing, the first computer to reach exaFLOPS was the Folding@Home project where computer users worldwide, including myself contribute to protein folding simulations for medical research).

I was idly browsing eBay recently (as you do) and stumbled on the wide sale of bits and pieces from some of these earliest computers. Owning a little bit of this history, if for no other use than a paperweight appealed, so parted with a few tenners for two modules. These were a memory core and processing unit from what is widely regarded to be the first supercomputer, the Control Data Corporation CDC 6600. Many of us will have seen photos of the old ferrite memory cores from these computers but have never handled one myself and also offered an interesting macro study.

The memory board measures 10.6 x 10.6 cm and the memory array 4.8 x 4.8 cm using a grid of 32 x 32 cores. A Canon 5600F A4 flatbed scanner was used to take the image, the CCD designs have enough depth of field to image flat subjects such as these, unlike the LED based scanners (see this Micscape article that compares the two types of scanner). It is a 4 kb memory board, compare this with the tiniest modern memory cards with many orders of magnitude more memory.

Close up of the core array using the Microscope mode of an Olympus TG5 compact camera. This takes a stack of five images and combines them in the camera. Another camera option allows a stack of thirty images to be taken for out of camera processing. Attempts to use my stereo to take an image stack and using CombineZP produced many artefacts.
Each core is ca. 0.75 x 0.15 mm and five wires run through each. A narrator of a YouTube video describing their construction remarks that the smallest cores were ca. '15 mil' i.e. 15/1000th of an inch or 0.38 mm, so about half this size! They are a marvel of micro-assembly. Some were hand built using a microscope but the process was later semi-automated. Reducing the core size allowed faster switching, higher memory density and reduced currents and thus smaller power requirements.
A 0 or 1 was stored as the clockwise / anticlockwise magnetisation of each core, dependent on the direction of current. A single core could be addressed by passing only half the current required to change its state so only at an intersection of one core would there be enough current. The other wires had other functions including reading the state and restoring the original state of each core after reading as this was lost by reading.

An intriguing variant of magnetic core memory was core rope memory. This was read only memory where a wire either going through or around a core defined the bit state. It was used as reliable memory for program storage in early NASA probes to Mars and the Apollo Guidance Computer. The program itself was painstakingly threaded wire by wire around the core strings to store as bits in the memory.

Detail of the soldering which all looks clean and bright after almost sixty years.

A so-called Cordwood logic module. Almost 6 000 of these formed the single central processor supported by peripheral processors. It used silicon transistors recently offered by Fairchild Semiconductors which could be packed at greater density and had higher switching speeds than the formerly used germanium transistors. Typically 30 logic gates per module which had typically 64 transistors. The multi-pin connectors are at the rear, the front facing connectors are test points. The memory and processor boards were assembled into cube type modules (see Figure 4 in James Thornton's paper, link below). Removing heat from the densely assembled components of supercomputers remains a major design consideration to this day. The sturdy front metal support was connected to a frame cooled by Freon.

The transistors and resistors in each Cordwood module shown were elegantly assembled as two central facing boards. Orienting these for soldering must have been challenging? Olympus TG-5 five image stack in microscope mode using its dedicated flash ring.

The CDC 6600 (Wikimedia Creative Commons image from the CDC 6600 entry, image credited to Jitze Couperus). The four cabinets, two front facing shown, are in the shape of a cross as even in 60s computers the length of wires were minimised as they had an effect on computer speed. Its use of two cathode ray tubes replaced the array of flashing status lights often seen on early computers. The cooling controls and circuits can be seen on the far right. It was released in 1964 and for most of the 60s remained the fastest, its successor the 7600 outperformed it. The 6600 was three times faster than the former top dog, the IBM 7030. Early adopters were the Lawrence Livermore National Laboratory and the Los Alamos National Laboratory.

The CDC 6600 had a speed of up to 3 megaFLOPS, my Apple iPhone 7 using the 'Mobile LinPack' app has a speed of 4.27 gigaFLOPS. So about a thousand times the power in the palm of my hand. What will the handheld computational firepower be in another sixty years?

Selected resources and further reading
There are a wealth of resources online on early history of supercomputers, both articles and videos. A selection that found valuable and some books are below.

Wikimedia CDC 6600 entry.
Encyclopedia of Computers and Computer History, Volume 1, edited Raúl Rojas, Fitzroy Dearborn Publishers, 2001, 'Core Memory' entry, page 198.
The Story of the Computer. A Technical and Business History, Stephen J Marshal. Print edition 2017.
The CDC 6600 Project by James E Thornton, Annals of the History of Computing, Vol. 2, no. 4, October 1980, 338-348.
Design of a Computer, The Control Data 6600, by J E Thornton, pub. Scott, Foresman and Company 1970. Released with the permission of the family into the public domain (pdf download).
Core Memory, Explained and Demonstrated, YouTube video by 'CuriosMarc', 24 mins uploaded Feb 2019. A very clear explanation and history of its development and principles of operation.

 

Comments to the author David Walker are welcomed.

 

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